1. Field of the Invention
The present invention relates to a memory system, a sense amplifier, a use, and a method for error detection via parity bits of a block code.
2. Description of the Background Art
U.S. Pat. No. 4,453,251 discloses a memory with an error correction. An option for error correction is the use of a block code. The Hamming code is a prior-art block code used for memories. The Hamming code encodes data and stores these as code words in a memory. Each individual code word has data bits and a plurality of parity bits (check bits). When the code words are read, the Hamming code is checked to determine whether it is a valid code. In the case of error, the bit in error in the code word is corrected by means of the Hamming error correction procedure. According to U.S. Pat. No. 4,453,251, the Hamming approach is unattractive, because the memory capacity must be substantially increased in order to accommodate the data bits and the parity bits of each code word. Alternatively, U.S. Pat. No. 4,453,251 proposes a memory array with lines and columns each with a parity bit for each column and a parity bit for each line.
European Pat. No. EP 0 926 687 A1, which corresponds to U.S. Pat. No. 6,275,960, provides a method for self-test and correction of errors. In the method for error correction, the lines (rows) for all columns must be read out. The rows are read out in their sequence, starting with row 0, and the single parity bit of the row is verified. In the case of error, the corresponding row is marked by a flag and a procedure to check the column parity is started.